The present invention generally relates to simulation of electronic systems, and more particularly to simulating operation of a communication bus.
Many bus architectures are complicated, and therefore require an advanced simulation environment for testing. Once a design for a system is complete, it is desirable to identify and fix problems by simulating operation of the system before building the actual system. Example simulation tools include Verilog-XL from Cadence and ModelSim from Model Technology.
In addition to a simulation tool, a suitable test bench must be created which is functional with both the system design and with the simulation tool. For some popular bus architectures for which bus core logic is commercially available, a number of vendors provide test benches. The commercially available test benches relieve the user from having to recreate what others have already created.
A user planning to purchase a test bench along with the bus core logic may reasonably expect some level of assurance that the bus core logic and test bench are functional. That is, the user wants to be assured that the test bench exercises the functionality of the bus and that the bus operates correctly. One method for providing such assurance to a customer is to demonstrate the test bench in operation. However, such a demonstration requires not only a functional system design, but also the live test bench.
The complexity of a test bench, along with the popularity of a particular bus architecture, are in part what make a test environment valuable. For example, the Peripheral Component Interface (PCI) bus architecture is a relatively complicated architecture whose use is widespread. Thus, the bus core logic as well as the test benches for PCI are quite valuable.
The value of the bus core logic and test bench makes the vendor fearful of uncontrolled demonstrations of the bus core logic and test bench. For example, a vendor may be reluctant to send the test bench to a customer without some level of supervision over use of the test bench to prevent unlicensed use as well as examination by competitors. Therefore, a system and method that addresses the above identified problems would be desirable.
The present invention provides a method for demonstrating the simulation of a communications bus. In one embodiment, the method comprises simulating operation of a system that includes a communications bus, a first bus agent, a second bus agent, and recorder logic. Recorder logic records bus signals of the first and second agents as signal vectors. Playback logic is substituted for the recorder logic, and during playback the signal vectors recorded for the first and second agents are output as bus signals by the playback logic.
In another embodiment, the method includes a communications bus. The method comprises simulating operation of a system that includes a communications bus, a first bus agent, a second bus agent, and recorder logic. For each bus agent, respective base signal vectors are recorded, each base signal vector representing a set of states of the bus signals during a base interval of time. When a change in state of any of the signals of the base signal vector is detected during a second interval of time, a duration value is recorded for a duration of time between the base interval and the second interval and a new signal vector is recorded with the states of the bus signals as present during the second interval. The new signal vector is then used as the base signal vector and the second interval is used as the base interval, and the process is repeated.
According to another aspect of the invention, a system is provided for recording the simulation of a communications bus. The system comprises a simulator, bus logic, a plurality of bus agent logic elements, and a simulation controller. The bus logic defines operation of the communications bus and is hosted by the simulator. The bus agents are interfaced with the bus logic and are hosted by the simulator. Each bus agent includes recorder logic that stores signal vectors representing bus signals output by the bus agent. The simulation controller is interfaced with the plurality of bus agents and is arranged to exercise selected usage of the bus by the agents.
According to yet another aspect of the invention, a system for demonstrating a simulation of a communications bus is provided. The system comprises a simulator, bus logic, a plurality of stored signal vectors, and a plurality of player logic elements. The bus logic defines operation of the communications bus and is hosted by the simulator. Each of the plurality of stored signal vectors represents bus signals output during an associated interval of time during the simulation. The plurality of player logic elements are interfaced with the stored signal vectors and with the bus logic, and are hosted by the simulator. Each bus agent is arranged to read respectively associated ones of the signal vectors and provide the associated signal vectors as bus signals at the associated intervals of time.
In still another embodiment, an apparatus is provided for demonstrating this simulation of a communications bus. The apparatus comprises: means for simulating operation of a system including a bus and a plurality of bus agents; means for recording signal vectors respectively generated by the bus agents during simulation; means for reading during playback of the simulation the signal vectors recorded during the simulation; and means for providing as output on the bus the signal vectors read during playback.
In yet another embodiment, a method is provided that allows for both xe2x80x9clivexe2x80x9d and recorded agents wherein a xe2x80x9clivexe2x80x9d agent is one that responds to input stimuli (bus signals) and a recorded agent simply plays back a recorded signaling sequence. The method comprises simulating operation of a system that includes a communications bus, a first bus agent, a second bus agent, and recorder logic. Bus signals of the first agent are recorded as signal vectors by the recorder logic. For playback, playback logic is substituted for the recorder logic in the first bus agent, and the signal vectors recorded for the first bus agent are output as bus signals by the playback logic. The second bus agent remains live during both recording and playback. Thus both the recording and playback systems simulate the second agent""s operation.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.